Xilinx LOGICORE UG144 - Manual (Page 35)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 35
UG144 April 24, 2009
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Chapter 4
Designing with the Core
This chapter provides general guidelines for creating designs using the GEMAC core. To
work with the example design included with the GEMAC core, see the 1-Gigabit Ethernet
MAC Getting Started Guide.
General Design Guidelines
This section describes the steps required to turn a GEMAC core into a fully functioning
design integrated with user-application logic. Not all implementations require all the
design steps described in this chapter. The following sections discuss the design steps
required for various implementations. For best results, carefully follow the logic design
guidelines.
Design Steps
Generate the core from the Xilinx CORE Generator™. See Chapter 3, “Generating the
Core.”
Using the Example Design as a Starting Point
The GEMAC core is delivered through the CORE Generator with an HDL example design
built around the core, allowing the functionality of the core to be demonstrated using
either a simulation package or in hardware, if placed on a suitable board.
Figure 4-1 is a
block diagram of the example design. For more information about the example design, see
the 1-Gigabit Ethernet MAC Getting Started Guide.
The example design illustrates how to:
•
Instantiate the core from HDL.
•
Source and use the client-side interface ports of the core from application logic.
• Connect the physical-side interface of the core (GMII or RGMII) to device IOBs
creating an external interface. (See
Chapter 7, “Using the Physical Side Interface.” )
• Derive the clock management logic, as described in Chapter 10, “Clocking and
Resetting.”