Interfacing to other cores, Ethernet 1000base-x pcs/pma or sgmii core, Chapter 11: interfacing to other cores – Xilinx LOGICORE UG144 User Manual
Page 113: Chapter 11, “interfacing to other cores, Chapter 11
1-Gigabit Ethernet MAC v8.5 User Guide
113
UG144 April 24, 2009
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Chapter 11
Interfacing to Other Cores
Ethernet 1000Base-X PCS/PMA or SGMII Core
The GEMAC core can be integrated in a single device with the Ethernet 1000BASE-X
PCS/PMA or SGMII core to extend core functionality to provide the following:
1000BASE-X Physical Coding Sublayer (PCS) logic designed to the IEEE 802.3 specification
with either:
•
1000BASE-X Physical Medium Attachment (PMA) using a device-specific RocketIO™
transceiver.
♦
Virtex®-5 SXT and LXT devices use RocketIO GTP transceivers
♦
Virtex-5 FXT devices use RocketIO GTX transceivers
After the first introduction of a device-specific RocketIO transceiver, all subsequent
references use the generic term RocketIO transceiver.
•
1000BASE-X parallel Ten-Bit-Interface (TBI) for connection to external SERDES.
•
Alternatively, the Ethernet 1000BASE-X PCS/PMA or SGMII core can function as a
GMII to Serial-GMII (SGMII) bridge, meaning that this can be used to provide the
GEMAC core with an SGMII for serial connection to appropriate PHYs.
A description of the latest available IP Update containing the Ethernet 1000BASE-X
PCS/PMA or SGMII core and instructions for obtaining the IP Update can be found on the
. A full description of the Ethernet
1000BASE-X PCS/PMA or SGMII core is outside the scope of this document.