Know the degree of difficulty – Xilinx LOGICORE UG144 User Manual
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1-Gigabit Ethernet MAC v8.5 User Guide
37
UG144 April 24, 2009
General Design Guidelines
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Implementing the 1-Gigabit Ethernet MAC in Your Application
The example design can be studied as an example of how to do the following:
•
Instantiate the core from HDL.
•
Source and use the client-side interface ports of the core from application logic.
•
Connect the physical-side interface of the core (GMII or RGMII) to device IOBs to
create an external interface.
•
Derive the clock management logic.
After working with the example design, you can write your own HDL application, using
single or multiple instances of the GEMAC core. Client-side interfaces and operation of the
core are detailed later in this chapter. For more information, see:
•
Chapter 10, “Clocking and Resetting.”
•
Using the GEMAC core in conjunction with the Ethernet 1000BASE-X PCS/PMA or
SGMII core in
Chapter 11, “Interfacing to Other Cores.”
•
Using the GEMAC core in conjunction with the Ethernet Statistics core in
•
10 Mbps, 100 Mbps, 1 Gbps Ethernet FIFO in
Appendix A, “Using the Client-Side
You can synthesize the entire design using any synthesis tool. The GEMAC core is pre-
synthesized and is delivered as an NGC netlist (which appears as a black box to synthesis
tools).
Run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to
a Xilinx device. Care must be taken to constrain the design correctly, and the UCF
produced by the CORE Generator should be used as the basis for the your own UCF. See
Chapter 9, “Constraining the Core,”
You can simulate the entire design and download the bitstream to the target device.
Know the Degree of Difficulty
A 1-Gigabit Ethernet MAC implementation is challenging to implement in any technology,
and all applications require careful attention to system performance requirements.
Pipelining, logic mapping, placement constraints, and logic duplication are all methods
that help boost system performance.
to determine the relative level of difficulty associated with the Spartan® and
Virtex® device families. These designs relate to meeting the core required system clock
frequency of 125 MHz.