Xilinx LOGICORE UG144 - Manual (Page 39)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 39
UG144 April 24, 2009
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Chapter 5
Using the Client Side Data Path
This chapter provides general guidelines for creating designs using the GEMAC core,
including a detailed description of each client-side data flow interface of the core.
Definitions of the abbreviations used throughout the remainder of this chapter are defined
in
Table 5-1 .
Receiving Inbound Frames
Received Ethernet frames are presented to the client logic on the Receiver subset of the
Client-Side Interface. For port definition, see
“Receiver Interface,” on page 27 .
Normal Frame Reception
Figure 5-1 illustrates the timing of a normal inbound frame transfer. The client must be
prepared to accept data at any time; there is no buffering within the MAC to allow for
latency in the receive client. Once frame reception begins, data is transferred on
consecutive clock cycles to the receive client until the frame is complete. The MAC asserts
the rx_good_frame signal to indicate that the frame was successfully received and that
the frame should be analyzed by the client.
Table 5-1: Abbreviations Used in Timing Diagrams
Abbreviation Definition
DA Destination address; 6 bytes
SA Source address; 6 bytes
L/T Length/type field; 2 bytes
FCS Frame check sequence; 4 bytes