Yaskawa 120 Series I/O Modules - Manual (Page 214)

5 Register I/O Specifications
5.3.2 Register Output Modules
5-16
f) Data Output Timing
The data output timing is shown in the following diagram.
Fig. 5.2 Data Output Timing
T1 T2
Data
SEL1
SEL2
T3 T4
Valid data Valid data