Comtech EF Data SDM-9000 - Manual (Page 143)

SDM-9000 Satellite Modem Theory of Operation
Rev.4 5–15
The DDS performs the function of a VCO in an analog implementation, but can be easily
programmed to the desired center frequency via the local M&C. Another PLL is used to
generate the 1/3 data clock frequency (decoder clock) from the symbol clock. The
decoder clock PLL uses outputs of the rate exchange circuit to maintain the proper phase
relationship. The recovered decoder and symbol clocks are then used throughout the
demodulator.
The soft-decision Look Up Table (LUT) converts the digital I and Q data from the
analog-to-digital converters into 3-bit soft-decision values. The soft-decision values
represent the binary data that was transmitted from the modulator, and subsequently
corrupted by noise in the transmission channel. These values are then passed to the
following circuits:
•
Commutator
•
Depuncture
•
Ambiguity resolver
The soft-decision data is commutated into three parallel paths at 1/3 of the symbol rate.
The commutator is simply a three-stage shift register, the output of which is loaded into
the three parallel depuncture circuits on every third symbol clock.
The depuncture circuit inserts null symbols into the soft-decision data stream just prior to
the Viterbi decoders. The positions of the null symbols are dictated by the code rate in
use. Since additional symbols are inserted into the data stream, the decoder clock PLL is
also synchronized to the depuncture logic.
The demodulator can lock up with phase and/or depuncture pattern ambiguities.
Therefore, the ambiguity resolver cycles through every combination of these ambiguities
until the Viterbi decoders achieve synchronization.
Each of the Viterbi decoders receives two parallel code words (G0 and G1) which are
3-bit soft decision data out of the depuncture logic. In addition to the code words, null
symbol indicators are also received from the depuncture logic, which indicate to the
Viterbi decoder which symbols were punctured out at the encoder. This data is processed
by the k=7 Viterbi decoder algorithm embedded in the decoder. If, while the state metric
normalization rate is monitored, it exceeds a pre-defined threshold, the out-of-sync
condition is indicated. This indicator is fed back to the ambiguity resolution logic (see
above) so that all possible ambiguity states can be tried. The Viterbi decoders each
incorporate a BER monitor which the local M&C can interrogate for performance
monitoring. The corrected data is output to the differential decoders.
After the differential decoders, the three serial bit streams, as well as the 1/3 data clock,
are converted to differential ECL for transfer across the system motherboard to the
interface board.