Artesyn MVME4100ET Single Board Computer Installation and Use (June 2014) - Manual (Page 77)

Functional Description
MVME4100ET Single Board Computer Installation and Use (6806800K76F) 77
4.13.1 System Clock
The system clock is driven by an oscillator. The following table defines the clock frequencies.
4.13.2 Real Time Clock Input
The RTC clock input is driven by a 1 MHz clock generated by the Control and Timers PLD. This
provides a fixed clock reference for the MPC8548E PIC timers which software can use as a
known timing reference.
4.13.3 Local Bus Controller Clock Divisor
The Local Bus Controller (LBC) clock output is connected to the PLD but is not used by the
internal logic.
4.14 Reset Control Logic
There are multiple sources of reset on the MVME4100ET. The following sources generate a
board level reset:
 Power-up
 Reset switch
 Watchdog timer
 System control register (BRD_RST)
 VMEbus reset
A board level hard reset generates a reset for the entire SBC including the processor, local
PCI/PCI-X buses, Ethernet PHYs, serial ports, flash devices, and PLD(s). If the MVME4100ET is
configured as the VME system controller, the VMEbus and local Tsi148 reset input are also
reset.
Table 4-1 Clock Frequencies
SYSCLK Core MPX (Platform) DDR2
66.67 MHz 1.3 GHz 533 MHz 266 MHz