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3 processor, 4 i2c serial interface and devices, 3 processor 4.4 i2c serial interface and devices – Artesyn MVME4100ET Single Board Computer Installation and Use (June 2014) User Manual

Page 71: C serial interface and devices

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Functional Description

MVME4100ET Single Board Computer Installation and Use (6806800K76F)

71

4.3

Processor

The MVME4100ET is designed to support the MPC8548E processor. The processor is
configured to operate at 1.3 GHz core frequency with a corresponding 533 Mb DDR2 memory
bus.

The MVME4100ET supports the power-on reset (POR) pin sampling method for processor reset
configuration. The states of the various configuration pins on the processor are sampled when
reset is de-asserted to determine the desired operating modes. Combinations of pull-up and
pull-down resistors are used to set the options. Some options are fixed and some are selectable
at build time by installing the proper pull-up/pull-down resistor. Refer to the MPC8548E
reference manual, listed in

Appendix B, Related Documentation

,

Manufacturers’ Documents

on

page 115

for additional details and/or programming information.

4.4

I

2

C Serial Interface and Devices

The MVME4100ET provides the following on-board I

2

C serial devices connected to the

MPC8548E I

2

C controller 0 interface:

8 KB serial EEPROM for VPD

Two 64 KB serial EEPROMs for user configuration data storage

One 256 byte serial EEPROM on SO-CDIMM for SPD

Maxim DS1375 Real Time Clock

On-Semi ADT7146 temperature sensor

8 KB serial EEPROM on RTM VPD

The RTC implemented on the MVME4100ET provides an alarm interrupt routed to the
MPC8548E PIC through the control PLD. A DS32KHz temperature controlled crystal oscillator
provides the RTC clock reference. A battery backup circuit for the RTC is provided on-board.

The On-Semi digital temperature sensor measures the temperature of the board and also
connects to the temperature diode on the MPC8548E. The temperature sensor also provides
an alarm interrupt routed to the MPC8548E PIC through the control PLD.