Handling the board, Handling the board -3 – Altera Stratix II GX PCI Express Development Board User Manual
Page 9
Altera Corporation
Reference Manual
1–3
August 2006
Stratix II GX PCI Express Development Board
Introduction
Figure 1–1. Stratix II GX PCI Express Development Board
Handling the
Board
When handling the board, it is important to observe the following
precaution:
w
Static Discharge Precaution—Without proper anti-static
handling, the board can be damaged. Therefore, use anti-static
handling precaution when touching the board.
155.52 MHz
72 MB QDRII
(x36)
1.8V HSTL
88E1111
GigE PHY+RJ45
1.8V HSTL
TX/RX LEDs
User LEDs
1.8V/2.5V CMOS
156.250 MHz
100.000 MHz
512 MB Flash
MAX II Device
HMC Port A
Stratix II GX Device
HMC Port B
x8 PCIe Edge
Connector
SFP
A
SFP
B
1.8 V CMOS
6x XCVR
CMOS/L
VDS
4x XCVR (
1)
CMOS/L
VDS
1x XCVR
1x XCVR
8x XCVR
REFCLK
256 MB DDR2
SDRAM (x72)
1.8 V SSTL
Push-Button
Switches
1.8 V/2.5 V CMOS
Note to Figure:
(1) The 4x XCVR channels are only supported by Stratix II GX EP2SGX130 devices.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)