Altera Stratix II GX PCI Express Development Board User Manual
Page 52
2–42
Reference Manual
Altera Corporation
Stratix II GX PCI Express Development Board
August 2006
Standard Communication Ports
The high-speed mezzanine cards use the board-provided Samtec socket
connector header.
Figure 2–14
shows example mezzanine cards. The
top-left is a x8 PCIe female adapter (right-angle) and the top-right is an
ATCA mezzanine card (AMC) adapter. The lower two figures are Altera
daughter card (PROTO1) adapters, which are typically 3” wide and can
be any length upward.
hsmb_tx_d_p[8]
101
Y34
hsmb_tx_d_p[9]
107
AA32
hsmb_tx_n[0]
31
AR5
hsmb_tx_n[1]
27
AN5
hsmb_tx_n[2]
23
AU5
hsmb_tx_n[3]
19
AW7
hsmb_tx_p[0]
29
AR4
hsmb_tx_p[1]
25
AN4
hsmb_tx_p[2]
21
AU4
hsmb_tx_p[3]
17
AW6
Table 2–28. HSMC B Connector Pin-Out
Schematic Signal Name
Samtec Pin Number
Stratix II GX
Pin Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)