Altera Stratix II GX PCI Express Development Board - Manual (Page 3)

Altera Corporation iii
Preliminary
Contents
About this Manual
Revision History ......................................................................................................................................... v
How to Contact Altera ............................................................................................................................... v
Typographic Conventions....................................................................................................................... vi
Chapter 1. Introduction
General Description................................................................................................................................ 1-1
Board Features ................................................................................................................................... 1-1
Block Diagram ................................................................................................................................... 1-2
Handling the Board ................................................................................................................................ 1-3
Chapter 2. Board Components & Interfaces
Board Overview...................................................................................................................................... 2-1
Featured Device ...................................................................................................................................... 2-5
Device Support .................................................................................................................................. 2-6
I/O & Clocking Resources ............................................................................................................... 2-6
Clocking Circuitry ................................................................................................................................ 2-11
Configuration Schemes and Status LEDs .......................................................................................... 2-12
JTAG Configuration ........................................................................................................................ 2-12
FPP Configuration ........................................................................................................................... 2-14
Flash Memory Configuration File Storage ............................................................................. 2-17
MAX II CPLD Configuration Controller ................................................................................ 2-18
Status and Channel Activity LEDs ............................................................................................... 2-21
General User Interfaces........................................................................................................................ 2-22
Push Button Switches (S1 Through S4) ........................................................................................ 2-22
User-Defined DIP Switch (S5) ....................................................................................................... 2-23
User LEDs (D9 Through D16) ....................................................................................................... 2-23
Configuration DIP Switch .............................................................................................................. 2-24
Board-Specific LEDs ....................................................................................................................... 2-25
FPGA Transceiver Channel Activity LEDs ................................................................................. 2-25
Power, Configuration, and Traffic Activity LEDs ...................................................................... 2-26
Standard Communication Ports ......................................................................................................... 2-27
PCI Express Edge Connector Interface (J9) ................................................................................. 2-27
Gigabit Ethernet (GigE) Interface (RJ1) ........................................................................................ 2-29
SFP A and B Interfaces (J6 and J7) ................................................................................................ 2-34
High-Speed Mezzanine Connectors A and B Interface ............................................................. 2-36
JTAG Interface ................................................................................................................................. 2-44
Off-Chip Memory ................................................................................................................................. 2-44
DDR2 SDRAM ................................................................................................................................. 2-44
QDRII SRAM .................................................................................................................................... 2-49
Flash Memory .................................................................................................................................. 2-52