Altera Stratix II GX PCI Express Development Board User Manual
Page 49
Altera Corporation
Reference Manual
2–39
August 2006
Stratix II GX PCI Express Development Board
Board Components & Interfaces
lists HSMC B connector pin-out as well as cooresponding
Samtec and Stratix II GX pin numbers.
hsma_tx_p[4]
13
J4
hsma_tx_p[5]
9
L4
Table 2–28. HSMC B Connector Pin-Out
Schematic Signal Name
Samtec Pin Number
Stratix II GX
Pin Number
hsmb_clk_in_n1
98
W38
hsmb_clk_in_n2
158
AU38
hsmb_clk_in_p1
96
W39
hsmb_clk_in_p2
156
AU39
hsmb_clk_in0
40
W37
hsmb_clk_out_n1
97
AM33
hsmb_clk_out_n2
157
AE31
hsmb_clk_out_p1
95
AM34
hsmb_clk_out_p2
155
AE32
hsmb_clk_out0
39
AN22
hsmb_d[0]
41
AR22
hsmb_d[1]
42
AT22
hsmb_d[2]
43
AT21
hsmb_d[3]
44
AP22
hsmb_led_rx
N/A
AF25
hsmb_led_tx
N/A
AV33
hsmb_rx_d_n[0]
50
_AE36
hsmb_rx_d_n[1]
56
AE38
hsmb_rx_d_n[10]
116
AG35
hsmb_rx_d_n[11]
122
AH36
hsmb_rx_d_n[12]
128
AJ36
hsmb_rx_d_n[13]
134
AK35
hsmb_rx_d_n[14]
140
AL38
hsmb_rx_d_n[15]
146
AP38
hsmb_rx_d_n[16]
152
AT39
hsmb_rx_d_n[2]
62
AG39
Table 2–27. HSMC A Connector Pin-Out (Part 5 of 5)
Schematic Signal Name
Samtec Pin Number
Stratix II GX Pin Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)