Figure 2–15. power distribution system – Altera Stratix II GX PCI Express Development Board User Manual
Page 69
Altera Corporation
Reference Manual
2–59
August 2006
Stratix II GX PCI Express Development Board
Board Components & Interfaces
Figure 2–15. Power Distribution System
Custom
Dual
Output
Switching
Regulator
12 V
DC Input
14 V - 20 V
12V = PCIe Motherboard
12A Switching
Regulator
Module
12-V PowerNet
HMCA
HMCB
Cooling Fan
1.2-V Partial Plane
Stratix II GX VCCint
Stratix GX XCVR PCS
Marvell PHY
6A Switching
Regulator
Module
Linear
V
IN
V
BIAS
1.8-V Partial Plane
Stratix II GX VCCio
DDR2 SDRAM
QDRII SRAM
MAXII and FLASH
3.3-V Partial Plane
Stratix II GX VCCpd
HMCA, HMCB
SFPA, SFPB
Oscillators, Driver
VTT
PowerNet
Memory Termination
XCVR_VCCA
PowerNet
TXVR VCCA
XCVR_VCCHTX
PowerNet
XCVR VCCG
XCVR_VCCR
PowerNet
XCVR VCCR
XCVR_VCCT
PowerNet
XCVR VCCT
XCVR VCCL
VCCA
PowerNet
Stratix II GX
EPLL/FPLL
2.5-V
Partial Plane
Stratix II LVDS VCCio
Marvell PHY
6A Switching
Regulator
Module
3.3 V = PCIe Motherboard
0.9 V
VREF
3.3 V
2.5 V
1.5 V
12 V
1.8 V
5.0 V
1.2 V
3.3 V
33 mA
92 mA
33 mA
33 mA
1.2 V
33 mA
1.2 V
33 mA
1.2 V
33 mA
Linear
V
IN
V
BIAS
Linear
V
IN
V
BIAS
Linear
V
IN
V
BIAS
Linear
V
IN
V
BIAS
Linear
V
IN
V
BIAS
Linear
V
IN
V
BIAS
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)