Altera Stratix II GX PCI Express Development Board - Manual (Page 7)

Altera Corporation Reference Manual 1–1
August 2006 Stratix II GX PCI Express Development Board
1. Introduction
General
Description The Stratix ® II GX PCI Express development board provides a hardware
platform for developing and prototyping high-performance PCI Express
(PCIe)-based designs as well as to demonstrate the Stratix II GX device’s
embedded transceiver and memory circuitry.
With up to 16-integrated transceiver channels and support for
high-speed, low-latency memory access (via DDR2 SDRAM and QDRII
memory interfaces), the Stratix II GX PCI Express development board
provides a fully-integrated solution for multi-channel, high-performance
applications, while also using limited board space.
Through the use of Altera ® MegaCore ® functions (or other intellectual
property [IP] cores) and expansion connectors, you can enable the
inter-operability of the Stratix II GX embedded transceivers with
third-party, application-specific standard products (ASSPs) in either
point-to-point or switching and bridging applications.
Because the Stratix II GX embedded transceivers can implement the
entire PCIe interface on one device, the Stratix II GX PCI Express
development board offers a high-bandwidth, low-latency, power-
efficient PCIe solution with sufficient LEs for your applications.
To simplify the design process, Altera provides a PCIe reference design—
available from the Altera website—for use as either a design starting
point or an experimental platform. The reference design is designed and
tested by Altera engineers and distributed with the PCI Express
Development Kit, Stratix II GX Edition (ordering code:
DK-PCIE-2SGX90N).
Board Features
The board features the following major component blocks:
■ Off-chip memory
● DDR2 SDRAM
● QDRII SRAM
■ FPGA configuration
● MAX ® II CPLD and 16-bit page mode flash memory
● JTAG interface