Altera Stratix II GX PCI Express Development Board User Manual
Page 46
2–36
Reference Manual
Altera Corporation
Stratix II GX PCI Express Development Board
August 2006
Standard Communication Ports
hsma_clk_out_n2
157
T30
hsma_clk_out_p1
95
W32
hsma_clk_out_p2
155
T31
hsma_clk_out0
39
G22
hsma_d[0]
41
D22
hsma_d[1]
42
F22
hsma_d[2]
43
A22
hsma_d[3]
44
B22
hsma_led_rx
N/A
B31
hsma_led_tx
N/A
F29
hsma_rx_d_n[0]
50
J38
hsma_rx_d_n[1]
56
K37
hsma_rx_d_n[10]
116
L39
hsma_rx_d_n[11]
122
R36
hsma_rx_d_n[12]
128
M38
hsma_rx_d_n[13]
134
P39
hsma_rx_d_n[14]
140
T34
hsma_rx_d_n[15]
146
R38
hsma_rx_d_n[16]
152
T39
hsma_rx_d_n[2]
62
L36
hsma_rx_d_n[3]
68
M36
hsma_rx_d_n[4]
74
N37
hsma_rx_d_n[5]
80
P36
hsma_rx_d_n[6]
86
R34
hsma_rx_d_n[7]
92
T37
hsma_rx_d_n[8]
104
U36
hsma_rx_d_n[9]
110
N35
hsma_rx_d_p[0]
48
J39
hsma_rx_d_p[1]
54
K38
hsma_rx_d_p[10]
114
K39
hsma_rx_d_p[11]
120
R37
hsma_rx_d_p[12]
126
M39
hsma_rx_d_p[13]
132
N39
hsma_rx_d_p[14]
138
T35
Table 2–27. HSMC A Connector Pin-Out (Part 2 of 5)
Schematic Signal Name
Samtec Pin Number
Stratix II GX Pin Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)