Altera Stratix II GX PCI Express Development Board User Manual
Page 61
Altera Corporation
Reference Manual
2–51
August 2006
Stratix II GX PCI Express Development Board
Board Components & Interfaces
qdrii_d[6]
B25
qdrii_d[7]
M25
qdrii_d[8]
M26
qdrii_d[9]
G21
qdrii_k_n
G20
qdrii_k_p
F20
qdrii_q[0]
G13
qdrii_q[1]
F12
qdrii_q[10]
G12
qdrii_q[11]
F13
qdrii_q[12]
A11
qdrii_q[13]
B12
qdrii_q[14]
C13
qdrii_q[15]
A13
qdrii_q[16]
D14
qdrii_q[17]
G15
qdrii_q[18]
D19
qdrii_q[19]
C18
qdrii_q[2]
F14
qdrii_q[20]
C17
qdrii_q[21]
E15
qdrii_q[22]
A18
qdrii_q[23]
A17
qdrii_q[24]
C16
qdrii_q[25]
A16
qdrii_q[26]
F15
qdrii_q[27]
D17
qdrii_q[28]
D18
qdrii_q[29]
E18
qdrii_q[3]
E12
qdrii_q[30]
F17
qdrii_q[31]
D15
qdrii_q[32]
G16
qdrii_q[33]
G17
Table 2–32. QDRII SRAM Pin-Out (Part 3 of 4)
Schematic Signal Name
Stratix II GX Pin Number
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)