Components attached to each power rail, Components attached to each power rail -56 – Altera Stratix II GX PCI Express Development Board User Manual
Page 66
2–56
Reference Manual
Altera Corporation
Stratix II GX PCI Express Development Board
August 2006
Power Supply
Components Attached to Each Power Rail
Table 2–36
shows the components attached to each power rail voltage.
512-Mb flash
Configuration flash
1.8 V
EPM570 CPLD
Configuration flash
1.8 V
SFP A
3.3-V to module
3.3 V
SFP B
3.3-V to module
3.3 V
Cooling fan
Cooling fan
12 V
HSMC A
12-V to card
12 V
3.3-V to card
3.3 V
HSMC B
12-V to card
12 V
3.3-V to card
3.3 V
Note to
Table 2–35
:
(1)
Using pre-release EPS2GX device power calculator. Assumes x8 PCIe + Dual
6.25Gb/s mezzanine cards (1 x 6 and 1 x 4) and two SONET SFPs (20-channel
EP2SGX130 device).
Table 2–36. Power by Rail (Part 1 of 2)
Power Rail
Interface Name
1.2 V
FPGA – VCCINT
FPGA – VCCA (PLL)
FPGA – VCCT (XCVR TX)
FPGA – VCCR (XCVR RX)
FPGA – VCCP (XCVR PCS)
DVDD (digital)
Total
1.5 V
FPGA – VCCG (XCVR TX buffer)
Total
Table 2–35. Power By Component (Part 2 of 2)
Board Device
Interface Name
Voltage
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)