Altera Stratix II GX PCI Express Development Board User Manual
Page 48
![background image](https://www.manualsdir.com/files/763835/content/doc048.png)
2–38
Reference Manual
Altera Corporation
Stratix II GX PCI Express Development Board
August 2006
Standard Communication Ports
hsma_tx_d_n[4]
73
M31
hsma_tx_d_n[5]
79
N31
hsma_tx_d_n[6]
85
R31
hsma_tx_d_n[7]
91
T29
hsma_tx_d_n[8]
103
P28
hsma_tx_d_n[9]
109
K33
hsma_tx_d_p[0]
47
G33
hsma_tx_d_p[1]
53
J32
hsma_tx_d_p[10]
113
L34
hsma_tx_d_p[11]
119
P27
hsma_tx_d_p[12]
125
N34
hsma_tx_d_p[13]
131
P34
hsma_tx_d_p[14]
137
R33
hsma_tx_d_p[15]
143
T33
hsma_tx_d_p[16]
149
U34
hsma_tx_d_p[2]
59
K32
hsma_tx_d_p[3]
65
K30
hsma_tx_d_p[4]
71
M32
hsma_tx_d_p[5]
77
N32
hsma_tx_d_p[6]
83
P30
hsma_tx_d_p[7]
89
R30
hsma_tx_d_p[8]
101
N27
hsma_tx_d_p[9]
107
K34
hsma_tx_n[0]
31
C5
hsma_tx_n[1]
27
A7
hsma_tx_n[2]
23
E5
hsma_tx_n[3]
19
G5
hsma_tx_n[4]
15
J5
hsma_tx_n[5]
11
L5
hsma_tx_p[0]
29
C4
hsma_tx_p[1]
25
A6
hsma_tx_p[2]
21
E4
hsma_tx_p[3]
17
G4
Table 2–27. HSMC A Connector Pin-Out (Part 4 of 5)
Schematic Signal Name
Samtec Pin Number
Stratix II GX Pin Number
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)