Altera Quartus II Scripting User Manual
Quartus ii scripting reference manual
Table of contents
Document Outline
- Quartus II Scripting Reference Manual
- Contents
- About this Reference Manual
- 1. Introduction to the Quartus II Scripting Reference Manual
- 2. Command-line Executables
- quartus_asm
- quartus_cdb
- Usage
- --back_annotate=
- --bottom_up_scripts_output_directory[=
] - --bottom_up_scripts_virtual_input_pin_delay[=
] - --bottom_up_scripts_virtual_output_pin_delay[=
] - --create_companion[=
] - --disable_auto_global_promotion_in_bottom_up_scripts[=on|off]
- --export_database=
- --generate_bottom_up_scripts[=on|off]
- --generate_hc_files
- --generate_hc_pll_delay
- --hc_archive[=
- --hc_min_archive
- --hc_ready
- --hc_review
- --import_database=
- --include_all_logiclock_regions_in_bottom_up_scripts[=on|off]
- --include_design_partitions_in_bottom_up_scripts[=on|off]
- --include_global_signal_promotion_in_bottom_up_scripts[=on|off]
- --include_logiclock_regions_in_bottom_up_scripts[=on|off]
- --include_makefiles_with_bottom_up_scripts[=on|off]
- --include_pin_locations_in_bottom_up_scripts[=on|off]
- --include_project_creation_in_bottom_up_scripts[=on|off]
- --include_timing_assignments_in_bottom_up_scripts[=on|off]
- --include_virtual_input_pin_timing_in_bottom_up_scripts[=on|off]
- --include_virtual_output_pin_timing_in_bottom_up_scripts[=on|off]
- --include_virtual_pin_locations_in_bottom_up_scripts[=on|off]
- --include_virtual_pins_in_bottom_up_scripts[=on|off]
- --incremental_compilation_export[=<.qxp file>]
- --incremental_compilation_export_netlist_type=
- --incremental_compilation_export_partition_name[=
] - --incremental_compilation_export_routing[=on|off]
- --incremental_compilation_import[=on|off]
- --merge[=on|off]
- --mif_dependency=
- --netlist_type=
- --override_partition_netlist_type=
- --post_map[=on|off]
- --remove_existing_regions_in_bottom_up_scripts[=on|off]
- --update_mif
- --vqm[=<.vqm file>]
- --write_eqn_file[=<.eqn file>]
- --write_rcf_for_vqm[=on|off]
- quartus_cpf
- quartus_drc
- quartus_eda
- Usage
- --board_boundary_scan[=on|off]
- --board_signal_integrity[=on|off]
- --board_symbol[=on|off]
- --board_timing[=on|off]
- --formal_verification[=on|off]
- --format=
- --gen_script=
- --gen_testbench
- --glitch_filtering[=on|off]
- --output_directory=
- --resynthesis[=on|off]
- --simulation[=on|off]
- --timing_analysis[=on|off]
- --tool=<3rd-party eda tool>
- --user_compiled_simlib_dir=
- --vcd_tb_design_instance_name=
- --vcd_type=
- quartus_fit
- quartus_jbcc
- quartus_jli
- quartus_map
- Usage
- -l=
- --analysis_and_elaboration
- --analyze_file=
- --convert_bdf_to_verilog=<.bdf file>
- --convert_bdf_to_vhdl=<.bdf file>
- --effort=
- --enable_wysiwyg_resynthesis[=on|off]
- --family=
- --generate_cmp_file=
- --generate_functional_sim_netlist
- --generate_inc_file=
- --generate_inst_file=
- --generate_symbol=
- --ignore_carry_buffers[=on|off]
- --ignore_cascade_buffers[=on|off]
- --incremental_compilation=
- --lib_path=
- --optimize=
- --parallel[=on|off]
- --part=
- --partition=
- --source=
- --state_machine_encoding=
- --update_wysiwyg_parameters
- --verilog_macro=
- quartus_pgm
- quartus_pow
- quartus_sh
- quartus_si
- quartus_sim
- Usage
- -c=
- --cell_delay_model_type=
- --check_outputs[=on|off]
- --interconnect_delay_model_type=
- --memory_limiter[=on|off]
- --mode=
- --overwrite_waveform[=on|off]
- --perform_glitch_filtering=
- --power_vcd_output=
- --pvt_multicorner[=on|off]
- --pvt_temperature=
- --pvt_timing_model_type=
- --pvt_voltage=
- --rev=
- --saf_output=
- --simulation_results_format=
- --vector_comparison_rule_value_0=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_1=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_dc=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_h=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_l=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_u=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_w=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_x=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_z=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_source=
- quartus_sta
- quartus_stp
- quartus_tan
- Usage
- --check_constraints[=
- --combined_model[=on|off]
- --create_timing_netlist
- --datasheet[=
- --delay_annotation_only
- --do_min_analysis[=on|off]
- --dump_atom_generated_clocks
- --fast_model[=on|off]
- --fmax=
- --post_map
- --speed=
- --tao[=<.tao file>]
- --tao_summary
- --tco=
- --th=
- --timing_analysis_only
- --tpd=
- --tristate
- --tsu=
- --zero_ic_delays
- Common Options
- Compiler Options
- Parallel Processing Options
- Settings File Options
- Tcl Options