Example – Altera Quartus II Scripting User Manual
Page 625

Chapter 3: Tcl Packages & Commands
3–495
timing_assignment
© July 2013
Altera Corporation
Quartus II Scripting Reference Manual
Example
## Specify the required minimum and maximum input
## delays on the input pin named "ipin" relative to
## the rising edge of the reference clock named "clk1"
set_input_delay 2ns -to "ipin" -clk_ref "clk1"
## Or, equivalently,
set_input_delay 2ns -to "ipin" -clk_ref "clk1" -min -max
## Specify the required minimum input delay on
## the input pin named "ipin" relative to the
## falling edge of the reference clock named "clk1"
set_input_delay 2ns -to "ipin" -clk_ref "clk1" -min -clock_fall
## Specify the required maximum input delay on
## input pins with names that start with "i"
## except those that start with "ibus"
assignment_group "input_pins" -add_member "i*" -add_exception "ibus*"
set_input_delay 2ns -to "input_pins" -max
MHz
MegaHertz
GHz
GigaHertz
Time Unit
Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)