Example – Altera Quartus II Scripting User Manual
Page 585

Chapter 3: Tcl Packages & Commands
3–455
sta
© July 2013
Altera Corporation
Quartus II Scripting Reference Manual
The "Type" column in the report uses a symbol to indicate what type of delay occurs at that point in the
path.
Possible "Type" values are:
Example
project_open my_project
create_timing_netlist
read_sdc
update_timing_netlist
# show worst 10 paths for each earliest and latest arrival results
report_skew -from [get_ports input[*]] -to [get_registers *] -panel_name \
"Report Skew" -npaths 10 -greater_than_skew 0.100 -detail full_path
delete_timing_netlist
project_close
RR
Rising input, rising output
RF
Rising input, falling output
FR
Falling input, rising output
FF
Falling input, falling output
Value
Description
CELL
Cell delay
COMP
PLL clock network compensation delay
IC
Interconnect delay
iExt
External input delay
LOOP
Lumped combinational loop delay
oExt
External output delay
RE
Routing element (only for paths generated with the
-show_routing option)
uTco
Register micro-Tco time
uTsu
Register micro-Tsu time
uTh
Register micro-Th time
Value
Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)