Altera Quartus II Scripting - Manual (Page 71)

Chapter 2: Command-line Executables 2–45
quartus_map
© July 2013 Altera Corporation Quartus II Scripting Reference Manual
quartus_map
Quartus ® II Analysis & Synthesis builds a single project database that integrates all the design files in a
design entity or project hierarchy. Analysis & Synthesis includes Quartus II Integrated Synthesis, which
provides comprehensive Verilog HDL and VHDL language support, as well as support for Altera-specific
languages such as AHDL.
Usage
quartus_map [-h | --help[=] | -v]
quartus_map []
This command supports the following options:
Option Page
-c= ............................................................................................................................... 2–96
-f=................................................................................................................................. 2–92
-h............................................................................................................................................................... 2–92
-l=................................................................................................................................................. 2–46
-v ............................................................................................................................................................... 2–92
--64bit ....................................................................................................................................................... 2–92
--analysis_and_elaboration................................................................................................................... 2–46
--analyze_file= ................................................................................................................. 2–46
--convert_bdf_to_verilog=<.bdf file>.................................................................................................. 2–46
--convert_bdf_to_vhdl=<.bdf file> ...................................................................................................... 2–46
--effort= .............................................................................................................................. 2–46
--enable_wysiwyg_resynthesis[=on|off] ........................................................................................... 2–46
--family= ..................................................................................................................... 2–47
--generate_cmp_file=...................................................................................................... 2–47
--generate_functional_sim_netlist ....................................................................................................... 2–47
--generate_inc_file= ........................................................................................................ 2–47
--generate_inst_file= ....................................................................................................... 2–47
--generate_symbol= ........................................................................................................ 2–47
--help[=] ....................................................................................................................... 2–93
--ignore_carry_buffers[=on|off] .......................................................................................................... 2–47
--ignore_cascade_buffers[=on|off] ..................................................................................................... 2–47
--incremental_compilation=................................................. 2–47
--lib_path= .................................................................................................................................. 2–48
--lower_priority ...................................................................................................................................... 2–93
--optimize= .................................................................................................. 2–48
--parallel[=on|off].................................................................................................................................. 2–48
--part=...................................................................................................................................... 2–48
--partition=............................................................................................................................. 2–48
--rev=.......................................................................................................................... 2–96
--set= ................................................................................................................... 2–96
--source=........................................................................................................................... 2–49
--state_machine_encoding=................................ 2–49
--update_wysiwyg_parameters ........................................................................................................... 2–49
--verilog_macro=................................................................................................................... 2–49
--version................................................................................................................................................... 2–93