Altera Quartus II Scripting - Manual (Page 216)

3–86 Chapter 3: Tcl Packages & Commands
database_manager
Quartus II Scripting Reference Manual © July 2013 Altera Corporation
generate_bottom_up_scripts
Usage
generate_bottom_up_scripts [-bottom_up_scripts_output_directory
] [-disable_auto_global_promotion
] [-include_all_logiclock_regions
] [-include_design_partitions
] [-include_global_signal_promotion
] [-include_logiclock_regions
] [-include_makefiles ]
[-include_pin_locations ] [-include_project_creation
] [-include_timing_assignments
] [-include_virtual_input_pin_timing
] [-include_virtual_output_pin_timing
] [-include_virtual_pin_locations
] [-include_virtual_pins value>] [-remove_existing_regions ]
[-virtual_input_pin_delay ] [-virtual_output_pin_delay
]
Options
-bottom_up_scripts_output_directory : Option
to specify the destination directory for generated scripts
-disable_auto_global_promotion : Option to turn
off automatic global signal promotion in the lower levels
-include_all_logiclock_regions : Option to include
all LogicLock regions from top-level project in each script.
-include_design_partitions : Option to include design
partitions from top-level in lower-level projects
-include_global_signal_promotion : Option to
promote any top-level global signal to global in the lower-levels
-include_logiclock_regions : Option to include
LogicLock regions from top-level entity
-include_makefiles : Option to also generate makefiles in
addition to Tcl scripts
-include_pin_locations : Option to lock ports connected to
top-level IOs to the top-level location
-include_project_creation : Option to create the
lower-level project and appropriate directory structure
-include_timing_assignments : Option to include
timing assignments from top-level in lower-level projects
-include_virtual_input_pin_timing : Option to
include timing constraints representing maximum delay to all created virtual input pins
from the driving modules
-include_virtual_output_pin_timing : Option to
include timing constraints representing maximum delay from all created virtual output
pins to the destination modules
-include_virtual_pin_locations : Option to lock
created virtual pins to location assigned in top-level entity
-include_virtual_pins : Option to include virtual pin
creation on appropriate lower-level ports
-remove_existing_regions : Option to include commands
that remove any existing LogicLock regions in the lower-level