Altera Quartus II Scripting - Manual (Page 136)

3–6 Chapter 3: Tcl Packages & Commands
Quartus II Scripting Reference Manual © July 2013 Altera Corporation
get_rtl_pin_info rtl 3–277
get_rtl_pins rtl 3–278
get_simulation_memory_info simulator 3–361
get_simulation_time simulator 3–362
get_simulation_value simulator 3–363
get_sp_pin_list chip_planner 3–62
get_stack chip_planner 3–63
get_tile_power_setting chip_planner 3–64
get_timing_analysis_summary_results report 3–263
get_timing_edge_delay advanced_timing 3–19
get_timing_edge_info advanced_timing 3–20
get_timing_edges advanced_timing 3–21
get_timing_node_fanin advanced_timing 3–22
get_timing_node_fanout advanced_timing 3–23
get_timing_node_info advanced_timing 3–24
get_timing_nodes advanced_timing 3–26
get_timing_paths sta 3–418
get_top_level_entity project 3–218
get_user_option project 3–219
group_simulation_signal simulator 3–364
import_database database_manager 3–90
import_partition incremental_compilation 3–117
init_tk misc 3–177
initialize_simulation simulator 3–365
is_legal_delay_value advanced_timing 3–27
is_project_open project 3–220
list_path timing_report 3–503
list_sps chip_planner 3–65
load misc 3–178
load_package misc 3–179
load_report report 3–264
load_rtl_netlist rtl 3–280
locate sta 3–421
logiclock_back_annotate backannotate 3–31
make_ape_connection chip_planner 3–66
make_input_port chip_planner 3–67
make_output_port chip_planner 3–68
make_sp chip_planner 3–69
open_device jtag 3–159
Command Name Package Page