Altera Quartus II Scripting - Manual (Page 72)

2–46 Chapter 2: Command-line Executables
quartus_map
Quartus II Scripting Reference Manual © July 2013 Altera Corporation
This command includes help on the following topics:
Help Topic Page
arguments ............................................................................................................................................... 2–93
makefiles.................................................................................................................................................. 2–93
return_codes ........................................................................................................................................... 2–95
-l=
Refer to the help for --lib_path= on page 2–48
--analysis_and_elaboration
Option to check all the design files in a design for syntax and semantic errors, and perform a netlist
extraction.
--analyze_file=
Option to check the specified design file for syntax and semantic errors.
--convert_bdf_to_verilog=<.bdf file>
Option to create a Verilog Design File (.v) for the specified Block Design File (.bdf).
--convert_bdf_to_vhdl=<.bdf file>
Option to create a VHDL Design File (.vhd) for the specified Block Design File (.bdf).
--effort=
Option to select synthesis effort level.
The following table displays available values:
--enable_wysiwyg_resynthesis[=on|off]
Option to unmap WYSIWYG primitives during synthesis and remap the gates back to WYSIWYG LCELL
primitives.
This option is not applicable if Quartus ® II Integrated Synthesis is used.
Value Description
auto Maximum synthesis effort. This is the default value.
fast Synthesis process is streamlined to improve runtime at the cost of design performace and/or
resource usage. Use this option when the Fitter early_timing_estimate mode is used, or when a
fast-synthesis compilation is needed without the need to run the Fitter. When this option is used
with the regular Fitter, Fitter performance may decrease as fast-synthesis netlists take longer to
route.