Examples – Altera Quartus II Scripting User Manual
Page 79

Chapter 2: Command-line Executables
2–53
quartus_pgm
© July 2013
Altera Corporation
Quartus II Scripting Reference Manual
V, CV, VL, CVL, IV
B, CB, IB
R, RB, CR, CRB, IR, IRB
E, CE, IE
L, CL
S
in which:
* Serial FLASH Loader option only
** Cannot be used in combination with other options
Note: Specifying a
must specify a
Passive Serial chain. Each device in a multi-device chain must have a corresponding -o construction.
Examples
Option
Description
P
Program
R
Erase
L
Lock/Security Bit
I
Initialize Bridge Device*
V
Verify
B
Blank-check
C
ISP Clamp
E
Examine**
S
Skip/Bypass**
Behavior
Option Syntax
JTAG Program
-o pvb;file.pof -o pvbi;file.jic
JTAG Examine
-o e;file.pof;device_name -o ei;file.jic;device_name
Skip Device (JTAG Bypass
-o s;device_name
Passive Serial Program
-o file.sof
Active Serial Program
-o pl;file.pof
Passive Serial Chain
-o file1.sof -o file2.sof -o file3.sof
JTAG Chain
-o p;file1.pof -o s;file2.pof -o v;file1.pof@1 -o p;file2.pof@2
CDF
quartus_pgm -c byteblastermv[lpt1] file.cdf
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)