Altera SerialLite III Streaming MegaCore Function - Manual (Page 8)

Related Information
• Standard Clocking Mode on page 4-12
• Advanced Clocking Mode on page 4-13
Performance and Resource Utilization
The following table lists the resources and expected performance for different SerialLite III Streaming IP
core variations. These results are obtained using the Quartus II software targeting the Stratix V GX
(5SGXMA7H2F35C2), the Arria V GZ (5AGZME7K2F40I3L), and the Arria 10 (10AX115S1F45I1SGES)
FPGA device.
Note: The numbers of ALMs and logic registers in the following table are rounded up to the nearest 100.
Table 2-2: SerialLite III Streaming IP Core FPGA Performance and Resource Utilization
Device Direction
Clocking
Mode
Parameters
ALMs
Logic Registers
M20K
Number
of Lanes
Per-Lane
Data Rate
(Mbps)
ECC Primary Secondary
Arria
10
Source Standard 24 17400 Disabled 1984 3937 259 48
Standard 24 17400 Enabled 2818 5696 902 72
Advanced 24 17400 Disabled 2378 4009 219 87
Advanced 24 17400 Enabled 4003 8412 910 121
Sink Standard 24 17400 Disabled 2930 7409 373 48
Standard 24 17400 Enabled 3673 9047 1052 72
Advanced 24 17400 Disabled 4060 7363 452 0
Advanced 24 17400 Enabled 3860 9084 1083 72
Duplex Standard 24 17400 Disabled 4226 10838 561 96
Standard 24 17400 Enabled 5775 14442 1726 144
Advanced 24 17400 Disabled 6032 10836 623 87
Advanced 24 17400 Enabled 7266 16808 1996 193
UG-01126
2015.05.04
Performance and Resource Utilization 2-3
About the SerialLite III Streaming IP Core Altera Corporation
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