Altera SerialLite III Streaming MegaCore Function - Manual (Page 32)

• In the standard clocking mode (pure streaming), the decoding process checks the received data stream
to detect idle control words that the source application module inserts. When the sink application
module detects the idle control words, it deasserts the valid signal on the user interface until it receives
valid user streaming data.
• In the advanced clocking mode, the sink application module does not insert or delete any idle words.
Instead, the sink application module deasserts the output valid signal to indicate an absence of data
coming from the sink adaptation module.
Sink Adaptation Module
The sink adaptation module provides rate adaptation logic between the application module and the
Native PHY IP core or Interlaken PHY IP core. The adaptation module implements the following
functions:
• Rate adaptation—Uses the lane FIFO buffers to do rate matching and absorb any data jitter between
the lanes on the recovered clock. The FIFO buffers also transfer data between the lanes on the
recovered clock. It also handles the Interlaken core's bursty write requests to present the user with the
streaming interface. In standard clocking mode, the FIFO buffers also help transfer data between the
rx_coreclkin
and
user_clock
domains.
• Interlaken framing layer stripping—Strips Interlaken framing layer symbols and diagnostic control
words from the data stream.
• Non-user idle deletion—Strips off any non-user idle control words that the source adaptation module
inserts.
Lane Alignment Module
The lane alignment module interfaces with the Native PHY or Interlaken PHY IP core to access incoming
data. This module removes lane skew from the incoming serial data streams and aligns various lanes using
the Interlaken's synchronization marker. After alignment is achieved, the module continuously monitors
the synchronization markers in the Interlaken metaframes for any loss of alignment.
Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode
For Arria 10 devices, this block is an instance of the Native PHY IP core configured for Interlaken - RX
only operation. For lane rates from 15.625 to 17.4 Gbps, the PMA width for Interlaken mode is 64 bits.
For lane rates up to 15.625 Gbps, the PMA width is 40 bits.
For Stratix V and Arria V GZ devices, the Interlaken module is an instance of the Interlaken PHY IP core
configured for RX only operation, and is generated by the Quartus II parameter editor. The core requires
a Stratix V Transceiver Reconfiguration Controller for transceiver calibration. The interface size is
initially equal to the number of transceiver channels that the sink core uses, which is the number of lanes.
Related Information
• Arria 10 Transceiver PHY User Guide
For more information about the Arria 10 Native PHY IP core.
• Altera Transceiver PHY IP Core User Guide
For more information about the Interlaken PHY IP core.
4-8 Sink Adaptation Module
UG-01126
2015.05.04
Altera Corporation SerialLite III Streaming IP Core Functional Description
Send Feedback