Altera SerialLite III Streaming MegaCore Function - Manual (Page 57)

Figure 5-1: Design Example for Simplex Core in Standard Clocking Mode
Demo
Management
Avalon Master
Export Export UART
Reset Controller
Traffic
Generator
Traffic
Checker
Avalon Interconnect
Interval
Timer
NIOS II
CPU
RAM
LCD
Interface
JTAG
interface
Simplex Normal Clocking Variation
SerialLite III
Streaming
Sink
SerialLite III
Streaming
Source
Transceiver
Reconfiguration
Controller
Transceiver
Reconfiguration
Controller
Character
LCD
Control
mgmt_reset_n
SerialLite III Streaming
Link Tx
SerialLite III Streaming
Link Rx
Demo Control
Qsys Subsystem
Transmit PLL +
Source Transceivers
Reconfiguration
Interfaces
Demo Management
Interface
Sink Transceivers
Reconfiguration
Interfaces
JTAG Avalon Master
Figure 5-2: Design Example for Duplex Core in Advanced Clocking Mode
Avalon Master
Export Export UART
Reset Controller
Avalon Interconnect
Interval
Timer
NIOS II
CPU
RAM
LCD
Interface
JTAG
interface
Transceiver
Reconfiguration Controller
(Only for Stratix V Devices)
Character
LCD
Control
Demo Control
Qsys Subsystem
JTAG Avalon Master
SerialLite III
Streaming
Duplex
Demo
Management
Traffic
Generator
Traffic
Checker
Duplex Advanced Clocking Variation
fPLL
5-2 SerialLite III Streaming IP Core Design Example for Stratix V Devices
UG-01126
2015.05.04
Altera Corporation SerialLite III Streaming IP Core Design Guidelines
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