Altera SerialLite III Streaming MegaCore Function - Manual (Page 46)

Signal Width
Clock
Domain
Direction Description
error 3 or 4
user_
clock
Output This vector indicates an overflow in the source
adaptation module’s FIFO buffer.
• Bit 0: Source adaptation module’s FIFO
buffer overflow
• Bit 1: Source PPM-absorption module’s FIFO
buffer overflow
• Bit 2: An SEU error occurred and was
corrected (ECC enabled)
Don't care (ECC disabled)
• Bit 3: An SEU error occurred and could not
be corrected (ECC enabled)
Don't care (ECC disabled)
The width of this signal depends on the clocking
mode:
• 3: Standard clocking mode
• 4: Advanced clocking mode
crc_error_
inject
1 user_
clock
Input This signal forces CRC-32 errors when CRC-32
error injection is enabled in the transceiver
channels. The CRC-32 error injection is enabled
via the transceiver reconfiguration controller.
Table 4-7: SerialLite III Streaming IP Core Sink Core Signals
Signal Width
Clock Domain
Direction Description
core_reset 1
N.A.
Input Asynchronous master reset for the core.
Assert this signal high to reset the MAC
layer, except for the fPLL that us available in
standard clocking mode.
xcvr_pll_ref_
clk
1
N.A.
Input Reference clock for the transceivers.
user_clock 1
N.A.
Output Clock for data transfers across the sink core
interface in the standard clocking mode.
user_clock_
reset
1
user_clock
Output The core asserts this signal when the
core_
reset
signal is high and deasserts this signal
when the reset sequence is complete in the
standard clocking mode.
4-22 Signals
UG-01126
2015.05.04
Altera Corporation SerialLite III Streaming IP Core Functional Description
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