About the seriallite iii streaming ip core, Seriallite iii streaming protocol, About the seriallite iii streaming ip core -1 – Altera SerialLite III Streaming MegaCore Function User Manual
Page 6: Seriallite iii streaming protocol -1
About the SerialLite III Streaming IP Core
2
2015.05.04
UG-01126
The SerialLite III Streaming IP core is a high-speed serial communication protocol for chip-to-chip,
board-to-board, and backplane application data transfers. This protocol offers high bandwidth, low
overhead frames, low I/O count, and supports scalability in both number of lanes and lane speed.
The SerialLite III Streaming IP core incorporates a physical coding sublayer (PCS), a physical media
attachment (PMA), and a media access control (MAC) block. The IP core transmits and receives
streaming data through the Avalon-ST interface on its FPGA fabric interface.
Figure 2-1: Typical System Application
SerialLite III
Streaming
MegaCore
Function
SerialLite III
Streaming
MegaCore
Function
FPGA
FPGA
User
Logic
User
Logic
Serial Data
(Up to
24 Channels)
Transmission
Media Support:
- PCB (Chip-to-Chip)
- Backplane (Board-to-Board)
Data Processing
or
Management Board
ADC
or
System Board
Control Board
Interface Board
SerialLite III Streaming Protocol
The SerialLite III Streaming IP core implements a protocol which supports the transfer of high bandwidth
streaming data over a unidirectional or bidirectional, high-speed serial link.
The SerialLite III Streaming IP core has the following protocol features:
• Simplex and duplex operations
• Support for single or multiple lanes
• 64B/67B physical layer encoding
• Payload and idle scrambling
• Error detection
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