Reset, Link-up sequence, Reset -16 – Altera SerialLite III Streaming MegaCore Function User Manual

Page 40: Link-up sequence -16

The 64-bit PMA interface support the higher range data rates from 15.625 to 17 Gbps:
Lane Data Rate in Standard Clocking Mode = User Clock Frequency × 1.1 × 64 > Input Data Rate *

Interlaken Overheads
Note: Calculations with 40 and 64 for the lane data rate in standard clocking mode are for the PMA

width interfaces.
Using these calculations, the following overhead can be derived:
Transmission Overheads in standard clocking mode = 1.1

Note: Assuming maximum metaframe overhead with a metaframe size of 200, the standard clocking

mode overheads are independent of Interlaken overheads. For more details, refer to the SerialLite

III data efficiency calculator.

Tip: You can obtain the SerialLite III Streaming MegaCore Function Data Efficiency Calculator for 28

nm Altera devices from your local Altera sales representative or by emailing

[email protected]

Therefore, the lane rate in the standard clocking mode equals:
Lane Rate = Input Data Rate × 1.1
In the advanced clocking mode, the transmission overheads equals the Interlaken overheads because no

fPLL is present. Therefore, the lane rate in advanced clocking mode equals:
Lane Rate = Input Data Rate × Interlaken overheads

Reset

Each core has a separate active high reset signal,

core_reset

, that asynchronously resets all logic in the

core.
Each core also includes the Native PHY or Interlaken PHY IP reset signal,

phy_mgmt_clk_reset

. This

reset signal must be on the same clock domain as the clock used to drive the reconfiguration controllers,

phy_mgmt_clk

. The Native PHY or Interlaken PHY IP core requires the assertion of this reset signal to

synchronize with the reconfiguration controller reset signal.
Note: Altera recommends using the same reset signals for both the Native PHY or Interlaken PHY IP

core and the reconfiguration controller.

Link-Up Sequence

Refer to the topics on source and sink core link debugging for information about the transmit and receive

core link-up sequence.

Related Information

•

Source Core Link Debugging

on page 5-7

•

Sink Core Link Debugging

on page 5-9

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