Altera SerialLite III Streaming MegaCore Function - Manual (Page 15)

Note: If your design targets Arria 10 devices, the transceiver reconfiguration functionality is embedded
inside the transceivers. The
phy_mgmt
bus interface connects directly to the Avalon-MM dynamic
reconfiguration interface of the embedded Arria 10 Native PHY IP core. This interface is provided
at the top level.
Files Generated for Altera IP Cores
The Quartus II software generates the following IP core output file structure:
Figure 3-2: IP Core Generated Files
_tb.csv
_tb.spd
.cmp - VHDL component declaration file
.ppf - XML I/O pin information file
.qip - Lists IP synthesis files
.sip - Contains assingments for IP simulation files
.v or .vhd
Top-level IP synthesis file .v or .vhd
Top-level simulation file
.qsys - System or IP integration file
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
_generation.rpt - IP generation report
.debuginfo - Contains post-generation information
.html - Connection and memory map data
.bsf - Block symbol schematic
.spd - Combines simulation scripts for multiple cores
_tb.qsys
Testbench system file
.sopcinfo - Software tool-chain integration file
scripts>
IP variation files
_tb
testbench system
sim
Simulation files
synth
IP synthesis files
sim
simulation files
Simulator scripts
_tb
n
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
n
IP variation files
testbench files
Table 3-2: IP Core Generated Files
File Name Description
<my_ip>.qsys The Qsys system or top-level IP variation file. <my_ip> is the name
that you give your IP variation.
3-6 Files Generated for Altera IP Cores
UG-01126
2015.05.04
Altera Corporation Getting Started
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