Altera SerialLite III Streaming MegaCore Function - Manual (Page 60)

loopback. If you use the design example with another device or development board, you may need to
update the device setting and constraints.
You must use correct pin constraints when using the core in simplex mode or when using more than one
reconfiguration controller. The synthesized design typically includes a reconfiguration interface for at
least three channels because three channels share an Avalon-MM slave interface, which connects to the
Transceiver Reconfiguration Controller IP core. Conversely, you cannot connect the three channels that
share an Avalon-MM interface to different Transceiver Reconfiguration Controller IP cores or you will
receive a Fitter error.
Note: The clocks in the design-generated SDC file (seriallite_iii_streaming.sdc) are set to static
frequency. You should adjust these clocks to the frequency used for the design.
Related Information
Altera Transceiver PHY IP Core User Guide
More information about the Interlaken PHY IP core.
Design Example Compilation and Download
After generating the IP core design example, you can compile the design example for a SerialLite III
Streaming two lane loopback design. The design example files are located in the
<variation name>_example/seriallite_iii_sv directory.
Note: The design example consists of a Qsys subsystem and Nios II processor system. You must compile
both systems for the design example to operate correctly.
To compile the design example Qsys subsystem, perform the following steps:
1. Open a Nios II command window.
2. Change the project directory to /demo_control/.
3. Type the following command to set up the required libraries and compile the generated design
example:
>source build_demo_control.sh
4. In the Quartus II software, change the directory to /demo/ and open the seriallite_iii_streaming_
demo.qpf file.
5. Compile the seriallite_iii_streaming_demo project in the Quartus II software.
6. If you have the supported development kit, download the . sof file onto the board .
Refer to the Development Kits/Cables page of the Altera website for more information.
To compile the design example Nios II processor system, perform the following steps:
1. In a Nios II command window, change the directory to /demo_control/software.
2. Type the following command to compile the Nios II processor:
> source batch_script.sh
The script generates a demo_control.elf file under the /app/ directory. This file can later be downloaded
into the FPGA.
To download the design example and subsystem, and operate the design, perform the following steps:
1. Start the Quartus II software.
2. In the Tools menu, click Qsys.
3. In the Qsys Tools menu, click Nios Command Shell [gcc4] to launch the Nios II command shell.
4. Type the following command to download the demo_control.elf file into the FPGA on the board and
to specify the USB cable number (
$CABLE_NUMBER
):
>nios2-download -g -r $CABLE_NUMBER ../
demo_control/software/app/demo_control.elf
5. Type the following command to start a terminal connection with the board (using the same cable
number):
>nios2-terminal $CABLE_NUMBER
UG-01126
2015.05.04
Design Example Compilation and Download 5-5
SerialLite III Streaming IP Core Design Guidelines Altera Corporation
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