Altera SerialLite III Streaming MegaCore Function - Manual (Page 31)

Figure 4-7: SerialLite III Streaming Sink Core (Advanced Clocking Mode)
Application
Module
SerialLite III Streaming Sink
Transceiver Reconfiguration Clock
SerialLite III
Streaming Link
Adaptation
Module
Transceiver Reference Clock
Core Clock
Alignment
Module
Sink User Clock
Sink User Interface
Clock Domains
Note:
1. Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices.
PHY IP
Core (1)
Sink Clock Generator
The clock generator is similar to the clock generator in the source core, and is only instantiated in
standard clocking mode. The clock generator synthesizes the user clock (
user_clock
) and core clock
(
rx_coreclkin
) signals from the Native PHY IP core (Arria 10 devices) or Interlaken PHY IP (Stratix V
and Arria V GZ devices) core's output clock signal. The clock generator consists of a fractional PLL and a
state machine responsible for clock generation and reset sequencing.
• For lane rates < 15.625 Gbps and all Stratix V and Arria V GZ devices, the fPLL outputs the
user_clock/user_clock_rx
and
rx_coreclkin
based on fixed ratios determined by the SerialLite III
Streaming parameter editor.
• For 15.625 Gbps < lane rates < 17.4 Gpbs, the fPLL outputs the
user_clock/user_clock_rx
based on
a fixed ratio, however, the
rx_coreclkin
operates at the same frequency as
rx_clkout
.
Related Information
Source Clock Generator on page 4-4
Sink Application Module
The sink application module performs the following functions:
• Strips the Interlaken protocol bursts encapsulation from the received serial data stream and presents
the data to the user interface.
• Decodes idle control words inserted by the source application module when the data stream is not
available and mirrors the data unavailability at the source by deasserting the output valid signal at the
user interface.
The encapsulation stripping process removes burst control words that define the beginning and the end of
streaming data bursts from the data stream. This process adjusts the received data stream to repack the
data words into a contiguous sequence.
UG-01126
2015.05.04
Sink Clock Generator 4-7
SerialLite III Streaming IP Core Functional Description Altera Corporation
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