Altera SerialLite III Streaming MegaCore Function - Manual (Page 2)

Contents
SerialLite III Streaming MegaCore Function Quick Reference.........................1-1
About the SerialLite III Streaming IP Core........................................................2-1
SerialLite III Streaming Protocol............................................................................................................... 2-1
SerialLite III Streaming Protocol Operating Modes................................................................... 2-2
Performance and Resource Utilization.....................................................................................................2-3
Getting Started ....................................................................................................3-1
Installing and Licensing IP Cores..............................................................................................................3-1
OpenCore Plus IP Evaluation.................................................................................................................... 3-1
Specifying IP Core Parameters and Options............................................................................................3-2
SerialLite III Parameter Editor.......................................................................................................3-2
Arria 10 Designs...............................................................................................................................3-3
SerialLite III Streaming IP Core Parameters............................................................................................3-3
Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs................................3-5
Files Generated for Altera IP Cores...........................................................................................................3-6
Files Generated for Altera IP Cores (Legacy Parameter Editor)........................................................... 3-8
Simulating..................................................................................................................................................... 3-9
Simulating Altera IP Cores in other EDA Tools..........................................................................3-9
Simulation Parameters.................................................................................................................. 3-10
Arria 10 Simulation Testbench.................................................................................................... 3-12
Simulating and Verifying the Design..........................................................................................3-13
SerialLite III Streaming IP Core Functional Description..................................4-1
IP Core Architecture....................................................................................................................................4-1
SerialLite III Streaming Source Core.............................................................................................4-3
SerialLite III Streaming Sink Core.................................................................................................4-6
SerialLite III Streaming Duplex Core............................................................................................4-9
Arria 10 versus Stratix V and Arria V GZ Variations.................................................................4-9
Clock Domains...........................................................................................................................................4-10
Core Clocking.................................................................................................................................4-11
Core Latency...................................................................................................................................4-14
Transmission Overheads and Lane Rate Calculations......................................................................... 4-15
Reset.............................................................................................................................................................4-16
Link-Up Sequence......................................................................................................................................4-16
CRC-32 Error Injection ........................................................................................................................... 4-17
FIFO ECC Protection ...............................................................................................................................4-17
User Data Interface Waveforms.............................................................................................................. 4-17
Signals..........................................................................................................................................................4-19
TOC-2
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