Altera SerialLite III Streaming MegaCore Function - Manual (Page 11)

OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
Specifying IP Core Parameters and Options
Follow these steps to specify IP core parameters and options.
1. In the Qsys IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to
customize. The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files
in your project. If prompted, also specify the target Altera device family and output file HDL
preference. Click OK.
3. Specify parameters and options for your IP variation:
• Optionally select preset parameter values. Presets specify all initial parameter values for specific
applications (where provided).
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for generation of a timing netlist, simulation model, testbench, or example design
(where applicable).
• Specify options for processing the IP core files in other EDA tools.
4. Click Finish to generate synthesis and other optional files matching your IP variation specifications.
The parameter editor generates the top-level .qsys IP variation file and HDL files for synthesis and
simulation. Some IP cores also simultaneously generate a testbench or example design for hardware
testing.
The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files
in Project to manually add a
.qsys file to a project. Make appropriate pin assignments to connect ports.
SerialLite III Parameter Editor
Based on the values you set, the SerialLite III streaming parameter editor automatically calculates the rest
of the parameters, and provides you with the following values or information:
• Input data rate per lane
• Transceiver data rate per lane
• A list of feasible transceiver reference clock frequencies, one of which you select to provide to the core
• Information related to the core overheads
Important: If your design targets Stratix V or Arria V GZ devices, you cannot migrate your design to
Arria 10 devices automatically. For Arria 10 devices, the transceiver reconfiguration
functionality is embedded inside the transceivers. Therefore, you must re-instantiate the IP
core to target Arria 10 devices.
Related Information
SerialLite III Streaming IP Core Parameters on page 3-3
3-2 Specifying IP Core Parameters and Options
UG-01126
2015.05.04
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