Altera Avalon Verification IP Suite - Manual (Page 64)

May 2011 Altera Corporation Avalon Verification IP Suite User Guide
5. Avalon-MM Monitor
The Avalon-MM Monitor verifies Avalon-MM interfaces using SystemVerilog
assertions. In addition, it provides test coverage reports so that you can determine
when your test vectors provide sufficient test coverage for your component’s
functionality.
The Avalon-MM Monitor is implemented in SystemVerilog and uses the
SystemVerilog Assertion (SVA) language. The SVA language is supported by the
Synopsys VCS, and Mentor Graphics Questa simulators. If you are using ModelSim,
the monitor component still compiles and simulates, but the assertion checking is
disabled.
Figure 5–1 shows a testbench that uses an Avalon-MM Monitor to test components
with Avalon-MM interfaces. The monitor’s Avalon-MM Master interface is connected
to a component’s Avalon-MM slave interface, and an Avalon-MM Slave interface is
connected to a component’s Avalon-MM master interface. The test program
communicates with the monitor. The test program can use the monitor’s assertion
checking and coverage groups to ensure that all legal parameter values for the DUT’s
Avalon-MM interface are tested. The Avalon-MM Monitor also includes a transaction
collector feature to collect and monitor transaction status.
Figure 5–1. Testbench Using an Avalon-MM Monitor with Avalon-MM Interfaces
Testbench
Test Program
System Verilog with VMM
generator
object
instance
generator
object
instance
generator
object
instance
configu-
ration
transactor
Avalon-MM Monitor
M S S
Avalon-MM
Slave BFM
Avalon-MM
Master BFM
M
Assertion
Checking Test
Coverage
API Methods
Transaction
Collector
initial()