Altera Avalon Verification IP Suite - Manual (Page 18)

May 2011 Altera Corporation Avalon Verification IP Suite User Guide
1. Clock Source BFM
The Avalon Verification IP Suite includes a Clock Source BFM that you can use to
generate a clock signal for your testbench.
1 The Clock Source BFM is only supported in Qsys.
Parameters
Table 1–1 lists the parameter settings for the clock signal.
Application Program Interface
This section describes the API for the Clock Source BFM.
clock_start()
clock_stop()
get_run_state()
Table 1–1. Clock Source BFM Parameter Settings
Option Default Value Legal Values Description
Clock rate 10 — Specifies the clock rate in MHz.
Prototype: clock_start ().
Arguments: None.
Returns: void .
Description: Turns on the clock.
Prototype: clock_stop() .
Arguments: None.
Returns: void .
Description: Turns off the clock.
Prototype: get_run_state() .
Arguments: None.
Returns: bit .
Description: Returns the state of the clock source; 1=running, 0=stop.