Altera Avalon Verification IP Suite - Manual (Page 43)

2–2 Chapter 2: Avalon-MM Master BFM with Avalon-ST API Wrapper
Avalon Verification IP Suite User Guide May 2011 Altera Corporation
In Figure 2–1 , the API call interface and Avalon-ST call and return interface operate in
separate clock domains with av_clk synchronizing the FPGA logic and api_clk
synchronizing the Avalon-ST translation interface. The Avalon-ST interface, which is
not part of the actual hardware design, operates at much higher frequencies than the
Avalon-MM Master BFM interface, enabling 1000 API calls and returns to be issued to
the BFM per Avalon clock cycle.
For every function call in the BFM, there is a channel identifier that stores the fixed
mapping between channel number and the function.
<$install_dir>/ip/altera/sopc_builder_ip/verification/lib/
altera_avalon_components_pkg.vhd
defines the following function calls:
■ MM_MSTR_INIT
■ MM_MSTR_SET_RESP_TIMEOUT
■ MM_MSTR_SET_CMD_TIMEOUT
■ MM_MSTR_ALL_TRANS_COMPLETE
■ MM_MSTR_GET_CMD_ISSUE_QUEUE_SIZE
■ MM_MSTR_GET_CMD_PEND_QUEUE_SIZE
■ MM_MSTR_GET_RESP_QUEUE_SIZE
■ MM_MSTR_PUSH_CMD
■ MM_MSTR_POP_RESP
■ MM_MSTR_SET_CMD_DATA
■ MM_MSTR_SET_CMD_ADDRESS
■ MM_MSTR_SET_CMD_BYTE_ENABLE
■ MM_MSTR_SET_CMD_BURST_COUNT
■ MM_MSTR_SET_CMD_IDLE
■ MM_MSTR_SET_CMD_REQUEST
■ MM_MSTR_SET_CMD_RESERVED_1
■ MM_MSTR_GET_RESP_REQUEST
■ MM_MSTR_GET_RESP_DATA
■ MM_MSTR_GET_RESP_ADDRESS
■ MM_MSTR_GET_RESP_BYTE_ENABLE
■ MM_MSTR_GET_RESP_BURST_SIZE
■ MM_MSTR_GET_RESP_LATENCY
■ MM_MSTR_GET_RESP_WAIT_TIME
■ MM_MSTR_SET_CMD_INIT_LATENCY
■ MM_MSTR_SET_CMD_BURST_SIZE
With the exception of the API wrapper, the Avalon-MM Master BFM with Avalon-ST
API Wrapper component is identical to the Avalon-MM Master BFM. For more
information about this component, refer to
Chapter 1, Avalon-MM Master BFM .