Altera Avalon Verification IP Suite User Manual
Page 109
4–2
Chapter 4: Avalon-ST Sink BFM with Avalon-ST API Wrapper
Avalon Verification IP Suite User Guide
May 2011
Altera Corporation
For every function call in the BFM, there is a channel identifier, which stores the fixed
mapping between channel number and the function.
<$install_dir>/ip/altera/sopc_builder_ip/verification/lib/
altera_avalon_components_pkg.vhd
defines the following function calls:
■
ST_SINK_INIT
■
ST_SINK_SET_READY
■
ST_SINK_POP_TRANS
■
ST_SINK_GET_TRANS_IDLES
■
ST_SINK_GET_TRANS_DATA
■
ST_SINK_GET_TRANS_CHANNEL
■
ST_SINK_GET_TRANS_SOP
■
ST_SINK_GET_TRANS_EOP
■
ST_SINK_GET_TRANS_ERROR
■
ST_SINK_GET_TRANS_EMPTY
■
ST_SINK_GET_TRANS_QUEUE_SIZE
With the exception of the API wrapper, the Avalon-ST Sink BFM with Avalon-ST API
Wrapper component is identical to the Avalon-ST Sink BFM. For more information
about this component, refer to
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)