Altera Avalon Verification IP Suite - Manual (Page 110)

May 2011 Altera Corporation Avalon Verification IP Suite User Guide
5. Avalon-ST Monitor
The Avalon-ST Monitor verifies Avalon-ST interfaces using SystemVerilog assertions.
In addition, it provides test coverage reports so that you can determine when your
test vectors provide sufficient test coverage for your DUT functionality.
The Avalon-ST Monitor is implemented in SystemVerilog and uses the SystemVerilog
Assertion (SVA) language. The SVA language is supported by the Synopsys VCS, and
Mentor Graphics Questa. If you are using ModelSim, the monitor component still
compiles and simulates, but the assertion checking is disabled.
Figure 5–1 shows a testbench that uses an Avalon-ST Monitor to test components with
Avalon-ST interfaces. This figure illustrates that the monitor’s Avalon-ST source
interface is connected to the DUT’s Avalon-ST sink interface, and an Avalon-ST sink
interface is connected to the DUT’s Avalon-ST source interface. The test program
communicates with the monitor. It uses the monitor’s assertion checking and
coverage groups to assure that all legal parameter values for the DUT’s Avalon-ST
interfaces are verified.
Figure 5–1. Testbench Using an Avalon-ST Monitor with Avalon-ST Interfaces
Testbench
Test Program
generator
object
instance
generator
object
instance
generator
object
instance
configu-
ration
transactor
Avalon-ST Monitor
Src Snk Snk
Avalon-ST
Sink BFM Avalon-ST
Source BFM
Src
Assertion
Checking Test
Coverage
API Methods
Transaction
Collector
initial()