Timing, Timing –2 – Altera Avalon Verification IP Suite User Manual
Page 25
1–2
Chapter 1: Avalon-MM Master BFM
Functional Description
Avalon Verification IP Suite User Guide
May 2011
Altera Corporation
Timing
The timing diagram in
illustrates the sequence of events for an Avalon-MM
Master BFM driving interleaved writes and reads when the
readdatavalid
signal is
present. This diagram serves as a reference for the following discussion of API and
events.
Figure 1–2. Avalon-MM Master Driving Interleaved Write and Read Transactions
writedata[31:0]
D1
D3
CLK
read
transaction1
transaction2
trans3 trans4
write
T
init
T
init
S
ci_1
T
idle
S
ci_2
S
ci_3
S
ci_4
transactionid
waitrequest
byteenable[3:0]
T
wr
T
wt_1
T
wt_2
T
ID_4
writeresponse
writeid
ID_1
ID_3
readdatavalid
readdata
D2
D4
T
rl_1
T
rl_2
S
rc_4,
S
rc_2
S
atc
readresponse
readid
ID_2
ID_4
writeresponsevalid
T
wrl_1
S
rc_1
T
ID_1
T
ID_2
T
ID_3
S
rc_3
D2
D4
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)