Altera Avalon Verification IP Suite - Manual (Page 14)

May 2011 Altera Corporation Avalon Verification IP Suite User Guide
Section I. Introduction to Avalon
Verification IP Suite
The Avalon ® Verification IP Suite provides bus functional models (BFMs) to simulate
the behavior and to facilitate the verification of IP that includes the following
interfaces and components:
■ Avalon Memory-Mapped (Avalon-MM) master and slave interfaces
■ Avalon Streaming (Avalon-ST) source and sink interfaces
■ Conduit interfaces and Avalon Tri-State conduit (Avalon-TC) interfaces
■ Clock source and reset source
■ Interrupt source and sink
■ Custom instruction master and slave
■ External memory
This suite also provides the following monitors to verify the respective Avalon
protocols:
■ Avalon-MM monitor
■ Avalon-ST monitor
Advantages of Using BFMs and Monitors
Using the Altera-provided BFMs and monitors has the following advantages:
■ It accelerates the verification process by providing key components of the
verification testbench.
■ It provides Avalon BFM components that implement the standard Avalon-MM
and Avalon-ST protocols, serving as a reference for those protocols.
■ For SystemVerilog users, it provides a platform that you can use to implement
constraint-driven randomized tests, including traffic scenario drivers, scoreboard
and coverage facilities, and assertion checkers.
Implementation of BFMs
The Avalon Verification IP Suite BFMs (excluding Clock Source and Reset Source
BFMs that are written in VHDL) are implemented in SystemVerilog. The BFM
components use primarily Verilog HDL with a few basic SystemVerilog constructs
that are supported by ModelSim
® -Altera Edition (AE). The monitor components use
the SystemVerilog Assertion (SVA) language and are supported only by simulators
that support SVA, including: Modelsim-Altera Starter Edition (ASE), Synopsys VCS,
and Mentor Graphics
® Questa.