Altera Avalon Verification IP Suite - Manual (Page 16)

Section I: Introduction to Avalon Verification IP Suite 1–3
In This User Guide
May 2011 Altera Corporation Avalon Verification IP Suite User Guide
As Figure 1–1 illustrates, it is possible to write a testbench using a traditional Verilog
HDL implementation or using SystemVerilog with VMM. For illustration purposes,
Figure 1–1 shows an Avalon-MM design under test (DUT) that includes both
Avalon-MM master and slave interfaces, and an Avalon-ST DUT that includes both
source and sink interfaces, although typical components might include a single
Avalon interface.
When verifying a component with Avalon-MM or Avalon-ST interfaces, a monitor is
inserted between the master or source BFM and the slave or sink interface of the DUT.
A second monitor can be interposed between the slave or sink BFM and the master or
source interface of the DUT. The monitors do not have to be placed between a BFM
component and another component. They can be inserted anywhere in the system to
provide protocol assertion checking and functional coverage reporting.
The test program drives the stimulus to the DUTs and determines whether the DUTs’
behavior is correct, by analyzing the responses. The BFMs translate the test program
stimuli, creating the signalling for the Avalon-MM and Avalon-ST protocols. The
monitors verify Avalon protocol compliance and provide test coverage reports.
In This User Guide
The Avalon Verification IP Suite User Guide provides a reference document for each of
the BFMs and Avalon Monitors. It includes the following sections:
■ Section II, Clock, Reset, and Interrupt BFMs
This section contains chapters that describe the parameters and API of the Clock
Source, Reset Source, Interrupt Source, and the Interrupt Sink BFMs.
■ Section III, Avalon-MM BFMs
This section contains chapters that describe the parameters, functional description,
and the API of the Avalon-MM Master and Slave BFMs. This section also includes
a tutorial on using the Avalon-MM BFMs.
■ Section IV, Avalon-ST BFMs
This section contains chapters that describe the parameters, functional description,
and the API of the Avalon-ST Source and Sink BFMs. This section also includes a
tutorial on using the Avalon-ST BFMs.
■ Section V, Conduit and External Memory BFMs
This section contains chapters that describe the blocks, parameters, and API of the
conduit, tri-state conduit, and the external memory BFMs.
■ Section VI, Nios II Custom Instruction BFMs
This section contains chapters that describe the blocks, parameters, and API of the
Nios II custom instruction master and slave BFMs.
■ Section VII, Tutorials
This section contains chapters that provide tutorials on how to use the BFMs to
verify IP interfaces and components in SOPC Builder and Qsys.