Figure 2–3. using instance names to define bfms – Altera Avalon Verification IP Suite User Manual
Page 176
Chapter 2:
Qsys Tutorial
2–
9
Verifying A
valon-ST D
U
T
May 20
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IP Suite U
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Guide
shows the simulation waveforms in the ModelSim-Altera software wave window.
Figure 2–3. Using Instance Names to Define BFMs
clk
reset_bfm.reset
clk_bfm_clk_clk
reset_bfm_reset_reset
src_data[31:0]
src_channel[2:0]
src_valid
src_startofpacket
src_endofpacket
src_error[2:0]
src_empty[1:0]
src_ready
st_in_data[31:0]
st_in_valid
st_in_ready
st_in_startofpacket
st_in_endofpacket
st_in_empty[1:0]
st_in_error[2:0]
st_in_channel[2:0]
st_out_data[31:0]
st_out_valid
st_out_ready
st_out_startofpacket
st_out_endofpacket
st_out_empty[1:0]
st_out_error[2:0]
st_out_channel[2:0]
sink_data[31:0]
sink_channel[2:0]
sink_valid
sink_startofpacket
sink_endofpacket
sink_error[2:0]
sink_empty[1:0]
sink_ready
00000002
XXXXXXXX
0
0
0
00000002
0
0
0
00000001
00000003
0
0
0
00000001
00000003
0
0
0
‘bXXX
‘bXXX
‘bXX
XXXXXXXX
‘bXX
‘bXXX
‘bXXX
‘bXX
‘bXXX
‘bXXX
XXXXXXXX
XXXXXXXX
‘bXXX
‘bXXX
‘bXX
Source BFM
DUT ( SC FIFO)
Sink BFM
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
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- LVDS SERDES (27 pages)
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- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- Floating-Point (157 pages)
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- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
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- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)