Altera Avalon Verification IP Suite - Manual (Page 102)

3–2 Chapter 3: Avalon-ST Sink BFM
Functional Description
Avalon Verification IP Suite User Guide May 2011 Altera Corporation
Functional Description
This section provides a functional description of the Avalon-ST Sink BFM. It includes
the following topics:
■ “Timing” on page 3–2
■ “Block Diagram” on page 3–3
Timing
The timing diagram shown in Figure 3–2 illustrates the timing for an Avalon-ST Sink
BFM signalling when it is ready to receive data from an Avalon-ST source. In the first
instance, the sink is not ready when the source has data. In the second instance, the
sink is ready but the source does not initially have valid data.
Table 3–1 describes the annotations used in Figure 3–2 .
Figure 3–2. Avalon-ST Source and Sink Timing
CLK
ready
valid
data D1 D2
S
snk_rdya
S
snk_rdyd
S
snk_rdyd
S
tr
S
snk_rdya
T
idle
T
idle
Table 3–1. Key to Annotations in Figure 3–2
Symbol Description
T
idle
The idle time between transactions. This time is reported by the command get_transaction_idles .
S
snk_rdya
Signals the sink has asserted ready . The event name is signal_snk_ready_assert .
S
tr
Signals the transaction has been received and queued. The event name is signal_transaction_received .
S
snk_rdyd
Signals the sink is not ready . The event name is signal_snk_ready_deassert .