Altera Avalon Verification IP Suite User Manual
Page 167

Chapter 1: SOPC Builder Tutorial
1–11
Verifying Avalon-MM Master DUT
May 2011
Altera Corporation
Avalon Verification IP Suite User Guide
shows the waveforms for the Avalon-MM master DUT write and reads to
the Avalon-MM Slave BFM component.
Figure 1–4. Avalon-MM Master Writes and Reads to Avalon-MM Slave BFM
clk
reset
error
master_waitrequest
master_address[31:0]
master_write
master_writedata[31:0]
master_read
master_readdata[31:0]
master_readdatavalid
master_byteenable[3:0]
clk
reset
avs_address[15:0]
avs_byteenable[3:0]
avs_waitrequest
avs_write
avs_writedata[31:0]
avs_read
avs_readdata[31:0]
avs_readdatavalid
4
8
12
0
4
8
12
16
2
6
14
x
0
x
2
x
6
x
14
x
F
0001
0002
0003
0000
0001
0002
0003
0004
F
2
6
14
x
0
x
2
x
6
x
14
x
Master DUT
(slave_bfm_tb.tb.
DUT.the_master)
Slave BFM
(slave_bfm_tb.tb.
DUT.the_slave_bfm)
0
0
0
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)