Altera ALTDLL - Manual (Page 97)

4–61 Chapter 4: Functional Description
Design Example: Implementing Half-Rate DDR2 Interface in Stratix III
ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation
7. Both outputs ( bidir_dq_0_output_hr_ddio_out_high_inst / dataout
and bidir_dq_0_output_hr_ddio_out_low_inst / dataout ) of the
previous DDIO_OUT ports are channeled into another DDIO_OUT port, which is
clocked at 333.333 MHz by the c1 PLL clock output.
8. The output bidir_dq_0_output_ddio_out_inst / dataout is then
connected to the bidirectional DQ output delay chain 1.
9. The output bidir_dq_0_output_delay_chain1_inst / dataout is
connected to the bidirectional DQ output delay chain 2, and the output
bidir_dq_0_output_delay_chain2_inst / dataout is connected to the
bidir_dq_io[0] pin.
10. The same data is propagated through the other inputs of
bidir_dq_hr_output_data_in[31:4] , which causes the
bidir_dq_io[7:1] pins to toggle in the same manner.
11. The throughput of data going out on each pin to the external memory is
666.666 Mbps.
12. The output delay chains are disabled. The
bidir_dq_0_output_delay_chain1_inst/datain ,
bidir_dq_0_output_delay_chain2_inst/datain ,
bidir_dq_0_output_delay_chain1_inst/dataout , and
bidir_dq_0_output_delay_chain2_inst/dataout signals are
aligned, which indicates that there’s no delay settings on
the two output delay chains.
The same write sequence applies to writing data with different delay chain values
activated on the two output delay chains. You can obtain the difference in the
delay chain values by analyzing the timing paths of the following signals:
■ bidir_dq_0_output_delay_chain1_inst/datain
■ bidir_dq_0_output_delay_chain2_inst/datain
■ bidir_dq_0_output_delay_chain1_inst/dataout
■ bidir_dq_0_output_delay_chain2_inst/dataout
■ bidir_dq_0_output_hr_ddio_out_high_inst/dataout
■ bidir_dq_0_output_hr_ddio_out_low_inst/dataout
■ bidir_dq_0_output_ddio_out_inst/dataout
■ bidir_dq_io[0]
1 For more information about how to analyze the timing paths to obtain the
delay chain values, refer to the timing diagrams in
“DQS_CONFIG /
IO_CONFIG Block” on page 4–22 .
13. The output path from the FPGA core to the bidirectional DQS pin is represented
by a 4-bit input, dqs_hr_output_data_in[3:0] . The OE path is 2 bits wide
from the FPGA core to the bidirectional buffer, dqs_hr_oe_in [1:0] . The input
path of the DQS pin goes through a specialized circuitry to clock the 8-bit
bidirectional DQ pin input paths.