Altera ALTDLL - Manual (Page 64)

Chapter 4: Functional Description 4–28
DQS_CONFIG / IO_CONFIG Block
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
Setting the Input Delay Chain to 750 ps Delay
Cursor 9 (1,755 ns) to cursor 10 (2,855 ns) in Figure 4–22 show that the input delay
chain is configured to 750 ps.
The config_clock takes 11 (1,100 ns) clock cycles to load the intended delay values
into the IO_CONFIG block because of the first four clock cycles (for the input delay
chain, D1), the next three clock cycles (for the output delay chain 2, D6) and the last
four clock cycles (for the output delay chain 1, D5).
The following steps describe how the input delay chain changes:
1. Because there is a 11-bit shift register in the IO_CONFIG block,
bidir_core_dq_confiq_enable(0) is asserted for 11 clock cycles. When the
shift registers are fully loaded, the shift registers have their bits arranges to
correspond with datain values.
2. The config_datain signal is asserted at the next 4 clock cycles to change the
input delay chain value.
3. The delay only takes effect when the config_update signal is asserted for one
clock cycle at 2955,000 ps (Cursor 11).
4. After the config_update signal is deasserted, the delay from
bidir_dq_0_input_delay_chain_inst/datain at 3230,000 ps (Cursor 13)
to bidir_dq_0_input_delay_chain_inst/dataout at 3230,750 ps (Cursor
14) is noticeable, which is 750 ps. Refer to Figure 4–23 .